New '4-D' Transistor Is Preview Of Future Computers

The research builds on previous work in which the team created a 3-D structure instead of conventional flat transistors. The approach could enable engineers to build faster, more compact and efficient integrated circuits and lighter laptops that generate less heat than today’s.

New findings show how to improve the device performance by linking the transistors vertically in parallel.

“A one-story house can hold so many people, but more floors, more people, and it’s the same thing with transistors,” Ye said. “Stacking them results in more current and much faster operation for high-speed computing. This adds a whole new dimension, so I call them 4-D.”

Findings will be detailed in two papers to be presented during the International Electron Devices Meeting on Dec. 8-12 in San Francisco. One of the papers has been highlighted by conference organizers as among “the most newsworthy topics and papers to be presented.”

The work is led by Purdue doctoral student Jiangjiang Gu and Harvard postdoctoral researcher Xinwei Wang.

The newest generation of silicon computer chips, introduced this year, contain transistors having a vertical 3-D structure instead of a conventional flat design. However, because silicon has a limited “electron mobility” – how fast electrons flow – other materials will likely be needed soon to continue advancing transistors with this 3-D approach, Ye said.

Indium-gallium-arsenide is among several promising semiconductors being studied to replace silicon. Such semiconductors are called III-V materials because they combine elements from the third and fifth groups of the periodic table.

The authors of the research papers are Gu; Wang; Purdue doctoral student H. Wu; Purdue postdoctoral research associate J. Shao; Purdue doctoral student A. T. Neal; Michael J. Manfra, Purdue’s William F. and Patty J. Miller Associate Professor of Physics; Roy Gordon, Harvard’s Thomas D. Cabot Professor of Chemistry; and Ye.

Transistors contain critical components called gates, which enable the devices to switch on and off and to direct the flow of electrical current. Smaller gates make faster operation possible. In today’s 3-D silicon transistors, the length of these gates is about 22 nanometers, or billionths of a meter.

The 3-D design is critical because gate lengths of 22 nanometers and smaller do not work well in a flat transistor architecture. Engineers are working to develop transistors that use even smaller gate lengths; 14 nanometers are expected by 2015, and 10 nanometers by 2018.

However, size reductions beyond 10 nanometers and additional performance improvements are likely not possible using silicon, meaning new materials will be needed to continue progress, Ye said.

Creating smaller transistors also will require finding a new type of insulating, or “dielectric” layer that allows the gate to switch off. As gate lengths shrink smaller than 14 nanometers, the dielectric used in conventional transistors fails to perform properly and is said to “leak” electrical charge when the transistor is turned off.

Nanowires in the new transistors are coated with a different type of composite insulator, a 4-nanometer-thick layer of lanthanum aluminate with an ultrathin, half-nanometer layer of aluminum oxide. The new ultrathin dielectric allowed researchers to create transistors made of indium-gallium- arsenide with 20-nanometer gates, which is a milestone, Ye said.

The work, based at the Birck Nanotechnology Center in Purdue’s Discovery Park, is funded by the National Science Foundation and the Semiconductor Research Corp.

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